Table of Contents

Blinking LED (ZYBO)

Sample

Power On

01. Check Jumper PIN-02 (USB)
02. Check Jumper PIN-21 (JTAG)
03. Connect USB
04. Power ON

Create Project

01. Open Vivado
02. Create New Project > Next
03. Select Project Directory
04. RTL Project + No Source
05. Part = xc7z010clg400-1
06. Summary > Finish

Source

01. Add Source
02. Add or Create Design Sources
03. Create File > Verilog > Name(LED.v) > Finish
04. Module (SW = input; LED = output) > OK
05. Design Sources (LED.v is added)
06. Source > Save
07. Check if no Syntax Error Files

LED.v

module LED(
    input SW,
    output LED
    ) ;
    assign LED = SW ;
endmodule

RTL Analysis

01. RTL Analysis > Open Elaborated Design > Schematic
02. Check RTL Schematic

Simulation

01. Add Source
02. Add or Create Simulation Sources
03. Create File > Verilog > Name(LED_TB.v) > Finish
04. Module (Nothing) > OK > Yes
05. Simulation Sources (LED_TB.v is added)
06. LED Test Bench > Save
07. Hierarchy (LED is added in LED_TB)

LED_TB.v

module LED_TB ;
    reg SW ;
    wire LED ;
    LED uut(
        .SW(SW),
        .LED(LED)
    ) ;
    initial begin
        SW = 1'b0 ;
        #100 SW = 1'b1 ;
        #200 SW = 1'b0 ;
        #300 SW = 1'b1 ;
        #400 SW = 1'b0 ;
    end
endmodule

08. Simulation Setting
09. Simulation Module Name > LED_TB
10. Run Simulation > Run Behavioral Simulation
11. Check Simulation Result

Synthesis

01. Run Synthesis > Synthesis Successfully Completed
02. Open Synthesized Design
03. Synthesis > Schematic

I/O Planning

01. Synthesis(Tab) > I/O Planning
02. Scalar Ports

03. File > Save Constraints > OK
04. Save Constraints > Name(LED.XDC)
05. Synthesis(Tab) > Default Layout
06. Run Synthesis > Synthesis Successfully Completed
07. View Reports

Implementation

01. Run Implementation > Implementation Successfully Completed
02. View Reports
03. Project Summary : Status = Complete

Bitstream

01. Generate Bitstream > Bitstream Generation Successfully Completed
02. View Reports

Open Hardware Manager

01. Open Hardware Manager > Open Target > Open New Target
02. Open Hardware Target > Next
03. Hardware Server Settings > Local Server > Next
04. Devices > xc7z010_1 > Next > Finish
05. Program Device > xc7z010_1 > LED.bit > Program
06. Check if green LED is on

Debug

01. SW on > LED on > OK

ARM Settings

01. Add Source
02. Add or Create Constraints
03. Add Files > zybo_master.xdc
04. Create Block Design > Name(HELLO) > OK
05. Diagram > Add IP > ZYNQ 7 Processing System > Change ZYNQ Chip to ZYBO
06. Double Click ZYNQ Chip
07. Import XPS Settings > zybo_zynq_def.xml > OK
08. M_AXI_GP0_ACLK(FPGA Input Clock) = FCLK_CLK0(Output Clock)
09. DDR > Make External
10. FIXED_IO > Make External
11. Validate Design > Validation Successful
12. Source > Design Source > HELLO > Create HDL Wrapper
13. Let Vivado Manage Wrapper and Auto Update
14. Generate Block Design > Generate
15. Generate Bitstrem
16. File > Export > Export Hardware > Include Bitstream > OK

Xilinx SDK

01. Workspace Settings
02. File > New > Other
03. Xilinx > Hardware Platform Specification > Next
04. Target Hardware Specification > HELLO_wrapper.hdf
05. File > New > Application Project > Name(FSBL) > Next > Zynq FSBL > Finish
06. File > New > Application Project > Name(WORLD) > Next > Hello World > Finish

sudo chmod 666 /dev/ttyUSB*
gtkterm -p /dev/ttyUSB1 -s 115200

07. WORLD/Debug/WORLD.elf > Run > Debug Configurations
08. Xilinx C/C++ Application (System Debugger) > New Launch Configuration
09. Debug
10. Confirm Perspective Switch > Yes
11. Resume
12. Print “Hello World”

References